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Dr.Rajesh Saha

Information

  • Designation : Assistant Professor
  • Email : rajesh@ece.nits.ac.in
  • Phone :

Key Notes

  • Journals: 2

2

PUBLICATIONS

1

PROJECT

Introduction [Biosketch]

  • Rajesh Saha Assistant Professor in the Department of Electronics and Communication Engineering, National Institute of Technology Silchar. Before joining NIT Silchar, he has worked as Assistant Professor at MNIT Jaipur from February 2020 to November 2023 and School of Electronics Engineering, VIT AP University, from May 2018 to February 2020. He has received B.E. with honours in Electronics and Telecommunication Engineering from Assam Engineering College, Guwahati, Assam in 2012 and M. Tech. in Mobile Communication and Computing from NIT Arunachal Pradesh, Yupia, in 2015. He has received Ph.D. in Electronics and Communication from NIT Silchar, Assam in 2018. His research interest includes Modeling and Simulation of Nanoelectronics Devices, Biosensors.

Institution Year Degree
NIT Silchar 2018 PhD
NIT ARunachal Pradesh 2015 M Tech
Assam Engineering College 2012 B E

Teaching Experience
Assistant Professor
21 November 2023 - 21 March 2025
NIT Silchar

Assistant Professor
27 February 2020 - 20 November 2023
MNIT Jaipur

Assistant Professor
9 May 2018 - 26 February 2020
VIT AP University

Industrial/Research Experience
Research Asoociate
5 March 2020 - 30 April 2020
NIT SIlchar

Awards And Honours

    • Enlisted in top 2% Scientist in the world list for given by Stanford University and Elsevier Year – 2024
    • Enlisted in top 2% Scientist in the world list for given by Stanford University and Elsevier Year – 2023
    • Received IEI Young Engineers Award 2022-23, given by The Institution of Engineers (India) Year – 2022
    • Best Paper Award for for Paper Presentation given by 4th Int. Conference DevIC 2021 Year – 2021
    • Best Session Paper Award for Paper presented at Micro 2020 given by 7th International Conference on Microelectronics, Circuits and Systems 2020 (Micro 2020), Year – 2020
    • Received B. E. with honors from Assam Engineering College
    • Secured 10th rank in “Mathematical Talent Search Examination” held on 2004
    • Recipient of Anundoram Borooah award in 2005

Sl.No: 1

Title Of Research Project: " Impact of Lateral Straggle on the Logic Gates, SRAM, and Ring Oscillator in Silicon on Insulator (SOI) Tunnel FET "

Sponsored By: SERB

Overall Budget: Rs 2308000

Duration: Dec 06, 2019 - Jun 06, 2022 (2 years 6 months)

Status: Completed

Principal Investigator: Dr. Rajesh Saha

Important Notice